Add/verilog courses #2151 (#2587)

* Update Verilog courses

Renamed `SystemVerilog` section to `Verilog / VHDL / SystemVerilog` because they are 3 different hardware description languages. Grouped them together so that all the Verilog resources can be found in one spot. Added new course as suggested in #2151

* Reorder Verilog courses by alphabetical order

* Add new course suggested by @mramdas

* Reorder Verilog courses
pull/2585/merge
Charlotte Tan 7 years ago committed by eshellman
parent a27f7be4b9
commit 7b332f6e76
  1. 16
      free-courses-en.md

@ -40,8 +40,8 @@
* [Scala](#scala) * [Scala](#scala)
* [Software Engineering](#software-engineering) * [Software Engineering](#software-engineering)
* [Swift](#swift) * [Swift](#swift)
* [SystemVerilog](#systemverilog)
* [Theory](#theory) * [Theory](#theory)
* [Verilog / VHDL / SystemVerilog](#verilog--vhdl--systemverilog)
* [Web Development](#web-development) * [Web Development](#web-development)
@ -337,18 +337,20 @@
* [Swiftris - Build an iOS Tetris app from scratch](https://www.bloc.io/swiftris-build-your-first-ios-game-with-swift) * [Swiftris - Build an iOS Tetris app from scratch](https://www.bloc.io/swiftris-build-your-first-ios-game-with-swift)
### SystemVerilog
* [SystemVerilog - Learn basics of SystemVerilog for Hardware Verification](https://verificationexcellence.teachable.com/p/learn-systemverilog)
* [SystemVerilog based UVM Methodology - Learn to build UVM based Testbenches in SystemVerilog](https://verificationexcellence.teachable.com/p/learn-ovm-uvm)
### Theory ### Theory
* [Automata Theory](https://lagunita.stanford.edu/courses/course-v1:ComputerScience+Automata+Fall2016/about) * [Automata Theory](https://lagunita.stanford.edu/courses/course-v1:ComputerScience+Automata+Fall2016/about)
* [Udacity: Intro to Theoretical Computer Science](https://www.udacity.com/course/intro-to-theoretical-computer-science--cs313) * [Udacity: Intro to Theoretical Computer Science](https://www.udacity.com/course/intro-to-theoretical-computer-science--cs313)
### Verilog / VHDL / SystemVerilog
* [SOC Verification Using SystemVerilog](http://verificationexcellence.in/online-courses/soc-verification-using-systemverilog)
* [SystemVerilog - Learn basics of SystemVerilog for Hardware Verification](https://verificationexcellence.teachable.com/p/learn-systemverilog)
* [SystemVerilog based UVM Methodology - Learn to build UVM based Testbenches in SystemVerilog](https://verificationexcellence.teachable.com/p/learn-ovm-uvm)
* [Verilog Hardware Description Language - An Introductory Course](http://vol.verilog.com/VOL/main.htm)
### Web Development ### Web Development
* [Discover Flask - Full Stack Web Development with Flask](https://github.com/realpython/discover-flask) * [Discover Flask - Full Stack Web Development with Flask](https://github.com/realpython/discover-flask)

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